Smartphones and tablets are
demanding more computing power, and chip company Adapteva hopes to bring
server-type performance to the devices with a chip it is announcing on Monday.
The Epiphany IV chip packs 64
cores, and can provide 70 gigaflops of performance while consuming one watt of
power, said Andreas Olofsson, Adapteva's CEO. A watt may be high for
smartphones, but performance and power consumed by the cores can be scaled down
to accelerate tasks such as hand-gesture recognition and face recognition,
Olofsson said.
The chip cannot host a full OS,
and is intended to be a co-processor to take processing load off CPUs. Epiphany
IV has a mesh design for faster data exchange, and the parallel cores have been
arranged in a square with multiple points of contact to receive and transfer
data. Cores can be easily added to scale performance, and the multiple
communication points help resolve bandwidth issues.
"We're not trying to take on Intel or ARM, we're trying
to sit next to it," Olofsson said.
Adapteva's mobile ambitions
follow an initial foray into the supercomputing space, where there has been an
interest in using the chip for grid-based tasks such as environmental modeling.
The company, which employs five people, already has one licensee, but Olofsson
declined to name it.
Beyond supercomputing, the
Epiphany IV's small size and low-power attributes make it a good co-processor
in smartphones and tablets, Olofsson said.
The company hopes to license the
chip design to mobile chip makers, and so far the reception has been positive,
Olofsson said. The accelerator could fit inside a system-on-chip, which
combines the CPU with a number of processors such as graphics and video
acceleration units.
"Our goal is to get into the next generation of smartphones
and tablets," Olofsson said.
The Epiphany IV is based on a
RISC (reduced instruction set computing) design, Olofsson said. The chip's
cores consume up to 25 milliwatts of power at peak performance, and the chip
for smartphones and tablets can have up to 64 cores. The chip will be made
using the 28-nanometer process, and provides an incremental power and
performance upgrade over its predecessor, which was made using the 65-nanometer
process. The previous chip, which was announced earlier this year, had 16 cores
and drew just under 1 watt of power.
The 64-core reference design of Epiphany IV will be
available the first quarter of next year, Olofsson said.
Adapteva's chip is not a general
purpose processor, and it differs from other accelerators such as the more
power hungry graphics processors, which accelerate certain scientific and math
applications, said Nathan Brookwood , principal analyst at Insight 64.
Adapteva's chip may also cost less than FPGAs (field-programmable gate arrays),
which are reprogrammable units designed to execute specific tasks such as XML
processing.
"The size of [Epiphany IV] cores is minuscule,"
Brookwood said. "Even if you have 64 cores, it's still a small chip."
However, Adapteva has more
opportunities in high-performance computing as supercomputers are increasingly
using accelerators to boost performance, Brookwood said. An Intel Xeon chip
with an Epiphany IV chip could potentially outperform a bunch of Xeon
processors, Brookwood said.
Adapteva will continue to chase
the high-performance computing market where supercomputers can take advantage
of Epiphany's parallelism, Olofsson said. Adapteva's chip can host applications
written using the OpenCL standard, a set of programming tools to develop and
manage parallel task execution. With OpenCL, programmers can write code once
for deployment across multiple computing environments. Apple, Nvidia, Intel and
Advanced Micro Devices are among the many companies backing OpenCL.
The Epiphany IV can scale up to 4,096 cores for a
high-performance computer, Olofsson said.
"It's not science fiction, we can do it, but we need a
customer to come and ask us to design it," Olofsson said.
Features
of the Epiphany architecture include:
- Complete
multicore solution featuring a high performance microprocessor ISA,
Network-On-Chip, and distributed memory system for seamless integration;
- Fully-featured
ANSI C/C++ programmable GNU/Eclipse based tool chain;
- High
Performance Superscalar RISC processor cores;
- IEEE
Floating Point Instruction Set;
- Shared
memory architecture with low-latency local memory at each processor node;
- 25
GB/sec local memory bandwidth;
- 6.4
GB/sec per processor network bandwidth;
- 70
GFLOPS/Watt energy efficiency;
- Processor
tile size of 0.13mm2 (with 32KB of SRAM); and
- Processor
tile max power of 25mW.
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